In general, an active matrix-type liquid crystal display device includes a liquid crystal panel composed of two substrates which sandwich a liquid crystal layer therebetween. On one substrate of the two substrates, a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines) are arranged in a grid shape, and there are provided a plurality of pixel formation portions arranged in a matrix shape so as to individually correspond to intersections of the plurality of gate bus lines and the plurality of source bus lines. Each of the pixel formation portions includes: a thin film transistor (TFT) that is a switching element in which a gate terminal is connected to the gate bus line passing through the intersection corresponding thereto and a source terminal is connected to a source bus line passing through the intersection concerned; a pixel capacitance for holding a pixel value; and the like. Moreover, on other substrate of the above-described two substrates, a common electrode that is a counter electrode provided commonly to the plurality of pixel formation portions is provided. In the active matrix-type liquid crystal display device, there are further provided: a gate driver (a scanning signal line drive circuit) that drives the plurality of gate bus lines; and a source driver (a video signal line drive circuit) that drives the plurality of source bus lines.
Video signals, each of which indicates the pixel value, are transmitted by the source bus lines; however, each of the source bus lines cannot transmit video signals indicating pixel values for a plurality of rows at a time (simultaneously). Therefore, writing of the video signals to the pixel capacitances in the above-mentioned pixel formation portions arranged in the matrix shape is sequentially performed one row by one row. Accordingly, the gate driver is constituted by a shift register, which is formed of a plurality of stages, so that the plurality of gate bus lines can be sequentially selected every predetermined period. Then, active scanning signals are sequentially outputted from the respective stages of the shift register (hereinafter, circuits which constitute the respective stages of the shift register are also referred to as “stage constituent circuits”), whereby the writing of the video signals to the pixel capacitances is sequentially performed one row by one row as mentioned above.
In the liquid crystal display device as described above, in some case, though a power supply thereof is turned off by a user, display is not cleared immediately, and an image like an afterimage remains. A reason for this is because, when the power supply of the device is turned off, a discharge path of electric charges held in each of the pixel capacitances is shut off, and residual electric charges are accumulated in each of the pixel formation portions. Moreover, when the power supply of the device is turned on in a state where the residual electric charges are accumulated in each of the pixel formation portions, then there occurs a deterioration in display quality, such as an occurrence of a flicker caused by a bias of impurities, the bias being based on the residual electric charges.
Accordingly, a liquid crystal display device is proposed, which is configured so that the residual electric charges in all of the pixel formation portions can be discharged by turning all of the gate bus lines into a selected state (active state) at the time of turning off the power supply and turning on the power supply (refer to WO 2009/028353). Note that a drive to turn all of the gate bus lines into the selected state is hereinafter referred to as an “all-selecting drive”.
In the liquid crystal display device disclosed in WO 2009/028353, a schematic configuration of the gate driver is as shown in FIG. 16. As mentioned above, the gate driver is constituted by the shift register made of the plurality of stages. Note that, in FIG. 16, stage constituent circuits SR(n−1) to SR(n+2) from an (n−1)-th stage to an (n+2)-th stage are shown. To each of the stage constituent circuits, there are inputted a set signal S, a reset signal R, a clock signal CK (one of a first gate clock signal GCK1 and a second gate clock signal GCK2), and an all-selecting signal ALL-ON. The set signal S is a signal for activating the stage constituent circuit, and the reset signal R is a signal for inactivating the stage constituent circuit. Moreover, a scanning signal OUT is outputted from each of the stage constituent circuits. The scanning signal OUT outputted from each of the stage constituent circuits is not only applied to the gate bus line corresponding thereto, but is also given as the set signal S to the stage constituent circuit on a subsequent stage, and is also given as the reset signal R to the stage constituent circuit on a preceding stage, as shown in FIG. 16. That is to say, the high-level scanning signal outputted from each of the stage constituent circuits activates the stage constituent circuit on the next stage, and inactivates the stage constituent circuit on the preceding stage. A schematic configuration of the stage constituent circuit is as shown in FIG. 17. In a logic unit, two signals (referred to as “Q signal” and “QB signal” for convenience) are generated. The Q signal controls a state of a switch SW1 in an output unit, and the QB signal controls a state of a switch SW2 in the output unit. From the output unit, the scanning signal OUT is outputted in accordance with states of the switch SW1, the switch SW2, the clock signal CK and the all-selecting signal ALL-ON.
In such a configuration as described above, at a usual time, the all-selecting signal ALL-ON is maintained at a low level (refer to FIG. 18). During the usual time, when the stage constituent circuit is inactive, the Q signal is at the low level, and the QB signal is at the high level. In this way, the switch SW1 turns to an OFF state, and the switch SW2 turns to an ON state, and accordingly, the scanning signal OUT turns to the low level. Meanwhile, during the usual time, when the stage constituent circuit is active, the Q signal is at the high level, and the QB signal is at the low level. In this way, the switch SW1 turns to the ON state, and the switch SW2 turns to the OFF state, and accordingly, the scanning signal OUT is at the high level during a period while the clock signal CK is being at the high level. From the above, at the usual time, clock signals (first gate clock signal GCK1 and second gate clock signal GCK2) having waveforms as shown in FIG. 18 are given to the gate driver, whereby the scanning signals outputted from the plurality of stage constituent circuits, which constitute the shift register in the gate driver, sequentially turn to the high level every predetermined period. Incidentally, if the all-selecting signal ALL-ON turns to the high level at the time when the switch SW1 is in the OFF state and the switch SW2 is in the ON state, then the scanning signal OUT outputted from this stage constituent circuit turns to the high level. Hence, when it is desired that the all-selecting drive be performed, the all-selecting signal ALL-ON is set at the high level, whereby all of the scanning signals can be set at the high level as shown in FIG. 18 in a state where the respective stage constituent circuits are inactive. In the way as described above, the residual electric charges in all of the pixel formation portions in the display unit are removed.